Intel wants EMIB to challenge TSMC in advanced packaging, but substrate costs could get in the way first. Taiwan’s Unimicron says its customer has provided commercial protection that will allow the substrate maker to earn a reasonable profit even when EMIB-T substrate yields fall below 50% during the ramp. Protecting the supplier does not make the scrap disappear: a substantial share of that cost could ultimately fall on Intel. The payer and allocation under the agreement have not been disclosed; that is an inference from the commercial arrangement.¹
If yields stay low, the savings Intel gains by avoiding a large silicon interposer could be eaten up by expensive substrates with embedded bridges. The costs do not stop there: chip bonding, power delivery, cooling and testing come after the substrate is made. To compete with TSMC, EMIB needs more than a good packaging yield. It has to carry the costs of the supply chain.
On November 1, Taiwan’s Economic Daily News reported overall Intel EMIB yields of approximately 60–65%, while the process of embedding silicon bridge dies in ABF substrates was at only 25–30%. The report compared those figures with roughly 98% for TSMC’s CoWoS.²³
Unimicron’s initial volume-production target for EMIB-T substrates is 50%. The ramp plan therefore has to account for a substantial amount of input that does not become a usable product.¹
EMIB connects computing chips and high-bandwidth memory (HBM) using small silicon bridges embedded in the substrate. Removing the large interposer shifts precision integration work to substrate manufacturers. Unimicron and Japan’s Ibiden are consequently central to whether Intel can expand supply. The price a customer ultimately pays will reflect both the savings and the costs of those manufacturing steps.
What Unimicron’s 50% target measures
At Unimicron’s July earnings briefing, chief marketing officer Julia Yang said EMIB-T substrates were expected to enter volume production in 2027. Six days earlier, Intel CEO Lip-Bu Tan said EMIB-T yield and reliability were reaching targets and that the company was moving toward high-volume production to support customers ramping in 2027. Intel was discussing technology and customer progress; Unimicron was discussing the substrates it must deliver. The substrate maker still has to turn a new process into repeatable production.¹¹⁶
At its July 29 briefing, Unimicron said it would work with two Japanese suppliers toward the initial 50% yield target.²² Supply chain reporting lists Unimicron, Ibiden and Shinko Electric Industries among the substrate suppliers.¹⁹
Intel’s process description shows the silicon bridge being placed in a cavity in the substrate, secured with adhesive, and then covered with dielectric and metal build-up layers. Bridge placement, connections to surrounding wiring and the stability of subsequent processing all affect the finished substrate. At its August briefing, Ibiden identified connections around the silicon bridge and fabrication of the core structure as technical challenges. It said the technology development phase was largely complete and that work was about to move into improving yields for volume production.²³
Intel’s architecture diagram shows EMIB bridges embedded in the substrate to connect adjacent dies, alongside Foveros vertical stacking. Source: Intel, Explaining Common Chip Terms.
Consider a simplified example. Of 100 substrates started, suppose only 50 pass inspection. The packaging facility attaches chips to those 50. The rejected substrates have consumed materials, labor and capacity, but their rejection has not also destroyed 50 sets of GPUs and HBM. Screening at this stage aims to catch defects before the expensive chips go on.
This is how low substrate yields can coexist with high downstream assembly yields. If assembly yield is measured from qualified substrates onward, earlier losses are already reflected in the cost of those substrates. They belong in the economics of the complete process.
Screening scrap early still leaves someone with the bill
If bridge-embedding yield stays around 30%, each usable substrate must carry a larger share of the scrap cost. How that expense feeds into package pricing will affect EMIB’s competitiveness.
Screening out bad substrates early avoids losing expensive GPUs and HBM with them, but it does not recover the materials and machine time already consumed. Suppose each batch costs the same to start and process, with no rework or salvage value. If yield falls from 50% to 25%, that portion of the cost allocated to each good substrate doubles. This is an illustrative calculation; actual losses also depend on when defects are discovered and whether they can be repaired.
Unimicron’s commercial protection allows it to remain profitable during the ramp, but it cannot make scrap, machine time and material costs disappear. Those expenses must be allocated through pricing or other commercial arrangements. For Intel, every good substrate delivered by a supplier could carry part of the cost of the failed ones.
Yield also consumes effective capacity. With the same equipment and input volume, halving the number of good substrates halves the number available for delivery. Doubling inputs to make up the difference requires more materials and processing time. Wealth Magazine’s reporting on the substrate industry describes tight supplies of glass cloth, copper foil and equipment, with customers coordinating the sequence of equipment deliveries to factories. Improving yields can free up delivery capacity on existing lines.⁹
After the substrate passes, the chips still have to work
The small silicon bridge carries dense wiring, but the chips above it still need to connect through fine contacts. Intel’s EMIB design uses a tighter contact pitch in the bridge region while allowing wider spacing elsewhere. During bonding, the chips and organic substrate must stay aligned under heat and pressure. Their materials expand at different rates, making deformation harder to control as packages grow larger.²
In an interview published by IEEE Spectrum on June 8, 2025, Rahul Manepalli, Intel’s head of substrate packaging technology, described work on low-temperature-gradient thermocompression bonding to address this mismatch. This takes place when chips are attached to the substrate. Even with a good substrate, the packaging equipment must form large numbers of reliable connections.¹⁵
Once those connections conduct, power delivery and signal quality face their own demands. Rapid changes in AI workloads can cause current surges and power noise. High-speed communication between HBM and the computing chips also requires sufficient design margin throughout the interconnect. EMIB-T adds through-silicon vias (TSVs) to the bridge for vertical power delivery to help address these constraints.⁵
Cooling also depends on assembly precision. If a large package warps, contact between the heat spreader and the chip surfaces can deteriorate. Manepalli described development work on heat spreaders assembled from separate pieces and on reinforcing structures to keep large packages flat at high temperatures. Intel said in that interview that these technologies were still in R&D and did not discuss commercialization dates.¹⁵
Testing comes next. Screening for known-good dies before packaging helps reduce the risk of losing expensive components together, but tests on individual dies have limits. Intel also uses system-level tests to simulate operating conditions and catch marginal defects that conventional tests may miss. Sound chip connections, performance of the complete product and long-term reliability each need to be verified.⁵
CoWoS substrates have yield challenges too
CoWoS-S puts dense interconnects on a large silicon interposer, which is then integrated with the package substrate. EMIB embeds local silicon bridges directly in the substrate. The two approaches place precision manufacturing work in different parts of the structure and require different assembly sequences.⁴
CoWoS itself has several variants. CoWoS-L uses local silicon interconnects (LSIs), redistribution layers (RDLs) and molding material to form an interposer. It, too, uses small pieces of silicon for the densest connections. Its bridges sit in the interposer, with a package substrate underneath.⁴
Intel estimates wafer-area utilization of roughly 90% for small silicon bridges, compared with about 60% for an interposer eight times the size of a lithography reticle field. Smaller components waste less area around the edge of a circular wafer. Those percentages do not yet measure the cost difference between finished, working packages: bridge embedding, bonding and testing all add further expense.⁵
TSMC’s earlier CoWoS research addressed warpage and yield in large packages. Its 2026 OCP presentation, under the heading “Component & System Level Risks for Diversified Substrate Sources,” described how glass-cloth shortages were widening the range of material sources. Differences in thermal expansion and stiffness across glass cloth and core materials affect package coplanarity, assembly yield and stress. Qualifying a new material source therefore requires checks at both package and system levels. CoWoS substrates may not have EMIB bridges embedded directly in them, but they still have to support large, power-hungry packages.¹¹¹²
The supplier networks overlap as well. TSMC has worked with Unimicron and Ibiden on substrate design technology files and design-for-manufacturing rules addressing problems such as stress concentrations. A chip company choosing a different advanced packaging provider may still depend on the same high-end substrate manufacturers and upstream materials.¹⁰
CoWoS production results and EMIB’s progress
At the 2026 OCP APAC Summit, TSMC disclosed that CoWoS at 5.5 times reticle size was in volume production with yields above 98%. Its technology page and annual report place that result within the CoWoS-L architecture, which uses local silicon interconnects. The competitor EMIB faces already uses small silicon bridges to scale up packaging.⁴¹²²¹
TSMC’s disclosed CoWoS production-yield benchmark. Source: Jun He, Advancing 3DIC Technologies to Propel AI Innovations, p. 9.
| Date in 2026 | Process or subject | Public statement and source |
|---|---|---|
| April 30 / May 3 | EMIB / EMIB-T validation | Wccftech cited Jeff Pu’s 90% figure; Kuo subsequently interpreted it as a technology-validation result. ²⁰¹³ |
| July 14 | EMIB-T; measurement scope unspecified | Wccftech reported a rumored 98% figure. ¹⁴ |
| July 23 | EMIB-T technology and customer ramps | Intel said yield and reliability were hitting targets and that it was moving toward high-volume production to support customer ramps in 2027. No percentage was given. ¹⁶ |
| July 29 briefing | Unimicron EMIB-T substrates | Initial 2027 target of 50%, as part of the volume-production plan. ¹ |
| August 1 | EMIB-T packaging / substrates | Wccftech cited unofficial claims of package yield approaching 90% and substrate yield around 50%. ¹⁷ |
| August OCP presentation | 5.5-times-reticle CoWoS | TSMC said it was in volume production with yield above 98%. ¹²²¹ |
| September 23 | EMIB substrates | TrendForce cited industry sources: roughly 30% in Q2 and about 45% more recently, with targets of 50% in Q4 and 60% in Q1 2027. ¹⁸ |
| October 22 | EMIB-T substrates | TrendForce cited industry sources: about 35% in Q3 against a year-end target of 50%. ¹⁹ |
| November 1 | Overall EMIB / silicon-bridge embedding in ABF substrates; product and measurement scope unspecified | Economic Daily News reported approximately 60–65% / 25–30%, alongside roughly 98% for CoWoS. ²³ |
On October 22, TrendForce cited supply chain sources placing Google HumuFish’s volume production in the first half of 2028.¹⁹
The original EMIB technology has been in volume production since 2017. Intel says assembly yields for its production designs are comparable to conventional flip-chip ball grid array (FCBGA) packages of similar complexity. That experience provides a base for new development. Delivering large EMIB-T packages at the cost and volume customers need still depends on scaling the new substrates, assembly processes and testing together.²⁸
Unimicron and Ibiden need to deliver consistent output
Through its long collaboration with Intel, Ibiden adopted Intel’s “Copy Exactly!” manufacturing method: use production equipment during development, then replicate the process across other lines once specifications are established. For substrates with embedded bridges, the value lies in maintaining quality across more equipment and batches after a process has been tuned successfully on one line.⁶
Ibiden’s October 30 presentation outlined technology priorities including larger substrates, more layers, complex core structures and embedded components to serve high-end GPUs and application-specific integrated circuits (ASICs). EMIB-T and other high-end substrate products draw on these same manufacturing resources.⁷
If bridge embedding is a major source of losses, improving its yield will increase the supply of good substrates. Bonding, power delivery, cooling and testing must then handle the higher volume. Ibiden also has to replicate a process established on one line across more equipment to support larger customer orders.
Intel can save on a large interposer by using small silicon bridges, but it cannot escape the cost of scrapped bridge-embedded substrates. As long as substrate yields remain low, every good EMIB product delivered consumes more materials and capacity. With supplier profitability protected, Intel has to show that those costs will not eat away the price advantage it needs to challenge CoWoS.
Sources
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Intel, Accelerating AI and HPC with Advanced Process and Packaging Technologies, pp. 5–6.
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IBIDEN, Financial Results of the 1st Half of FY2026, October 30, 2026, pp. 12–14.
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Yuanqing Lin, “A Full Account of the ABF Substrate Shortage,” Wealth Magazine, issue 771.
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TSMC, TSMC Announces Breakthrough Set to Redefine the Future of 3D IC, September 27, 2023, p. 2.
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Intel, Q2 2026 CEO/CFO Earnings Call Comments, July 23, 2026, p. 2.